In the design of a semiconductor memory device, redundant memory cells are generally manufactured together with the memory array along columns or rows of the memory array. A redundancy circuit is provided to control the replacement of one or more defective memory cells in the memory array with one or more of the redundant memory cells. The redundant memory cells allow the memory device to function properly even when there are defective memory cells in the memory array.
Generally, the redundancy circuit is connected to the redundant memory cells, and selects a column or row of redundant memory cells to replace a corresponding column or row of memory cells that has one or more defective cells. In particular, the redundancy circuit responds to an address signal that corresponds to a defective cell in the memory array by accessing a redundant memory cell instead of the defective cell.
A conventional redundancy circuit design uses fusible links for on a logic circuit to generate signals that effectuate the replacement of defective cells. The logic circuit may be consisted of an array of logic gates that have fusible links between the logic gates. The fusible link design allows the electrical connections between logic gates to be “programmed” by providing a large current to the one or more links to sever the fusible links. The logic circuit, programmed with specific remaining connections between logic gates, operates the redundancy circuit to permanently replace defective cells with redundant cells.
However, if the replacement redundant memory cell becomes defective at a later time, the permanency of the redundant circuit prevents the replacement redundant cell to be replaced, thereby limiting the reliability and flexibility of the memory device. As a result, the conventional redundancy circuit can only be used to replace defective memory cells resulted from the manufacturing process, and not memory cells that later became defective after the memory device is put to operation.